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dual 8-/10-/12-/14-/16-bit 250 msps digital-to-analog converters ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features high dynamic range, dual dacs low noise and intermodulation distortion single carrier wcdma aclr = 80 dbc @ 61.44 mhz if innovative switching output stage permits useable outputs beyond nyquist frequency lvcmos inputs with dual-port or optional interleaved single-port operation differential analog current outputs are programmable from 8.6 ma to 31.7 ma full scale auxiliary 10-bit current dacs with source/sink capability for external offset nulling internal 1.2 v precision reference voltage source operates from 1.8 v and 3.3 v supplies 315 mw power dissipation small footprint, pb-free, 72- lead lfcsp applications wireless infrastructure: wcdma, cdma2000, td-scdma, wimax wideband communications: lmds/mmds, point-to-point instrumentation: rf signal generators, arbitrary waveform generators general description the ad9741/AD9743/ad9745/ad9746/ad9747 are pin- compatible, high dynamic range, dual digital-to-analog converters (dacs) with 8-/10-/12-/ 14-/16-bit resolutions and sample rates of up to 250 msps. the devices include specific features for direct conversion transmit applications, including gain and offset compensation, and they interface seamlessly with analog quadrature modulators, such as the adl5370. a proprietary, dynamic output architecture permits synthesis of analog outputs even above nyquist by shifting energy away from the fundamental and into the image frequency. full programmability is provided through a serial peripheral interface (spi) port. in addition, some pin-programmable features are offered for those applications without a controller. product highlights 1. low noise and intermodulation distortion (imd) enables high quality synthesis of wideband signals. 2. proprietary switching output for enhanced dynamic performance. 3. programmable current outputs and dual auxiliary dacs provide flexibility and system enhancements. functional block diagram 16-bit dac1 16-bit dac2 interface logic gain dac gain dac offset dac offset dac internal reference and bias refio fsadj serial peripheral interface sdo sdio sclk csb 10 cmos interface clkp clkn pid<15:0> p2d<15:0> iout1p iout1n iout2p iout2n aux1p aux1n aux2p aux2n 06569-001 figure 1.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications.......................................................................... 5 digital and timing specifications.............................................. 7 absolute maximum ratings............................................................ 8 thermal resistance ...................................................................... 8 esd caution.................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 14 terminology .................................................................................... 17 theory of operation ...................................................................... 18 serial peripheral interface ......................................................... 18 general operation of the serial interface ............................... 18 instruction byte .......................................................................... 18 msb/lsb transfers .................................................................... 19 serial interface port pin descriptions ..................................... 19 spi register map ............................................................................ 20 spi register descriptions .............................................................. 21 digital inputs and outputs ........................................................... 22 input data timing ..................................................................... 22 dual-port mode timing ........................................................... 22 single-port mode timing ......................................................... 22 spi port, reset, and pin mode.................................................. 22 driving the dac clock input .................................................. 23 full-scale current generation ................................................. 23 dac transfer function ............................................................. 24 analog modes of operation ..................................................... 24 auxiliary dacs .......................................................................... 25 power dissipation....................................................................... 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 5/07revision 0: initial version
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 3 of 28 specifications dc specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i fs = 20 ma, full-scale digital input, maximum sample rate, unless otherwise noted. table 1. ad9741, AD9743, and ad9745 ad9741 AD9743 ad9745 parameter min typ max min typ max min typ max unit resolution 8 10 12 bits accuracy differential nonlinearity (dnl) 0.03 0.05 0.13 lsb integral nonlinearity (inl) 0.05 0.10 0.25 lsb main dac outputs offset error 0.001 0.001 0.001 %fsr offset error temperature coefficient 1.0 1.0 1.0 ppm/c gain error 2.0 2.0 2.0 %fsr gain error temperature coefficient 100 100 100 ppm/c gain matching (dac1 to dac2) 1.0 1.0 1.0 %fsr full-scale output current 8.6 31.7 8.6 31.7 8.6 31.7 ma output compliance voltage ?1.0 +1.0 ?1.0 +1.0 ?1.0 +1.0 v output resistance 10 10 10 m auxiliary dac outputs resolution 10 10 10 bits full-scale output current ?2.0 +2.0 ?2.0 +2.0 ?2.0 +2.0 ma output compliance voltage rangesink current 0.8 1.6 0.8 1.6 0.8 1.6 v output compliance voltage rangesource current 0 1.6 0 1.6 0 1.6 v output resistance 1 1 1 m monotonicity 10 10 10 bits reference input/output output voltage 1.2 1.2 1.2 v output voltage temperature coefficient 10 10 10 ppm/c external input voltage range 1.15 1.3 1.15 1.3 1.15 1.3 v input or output resistance 5 5 5 k power supply voltages avdd33, dvdd33 3.13 3.47 3.13 3.47 3.13 3.47 v cvdd18, dvdd18 1.70 1.90 1.70 1.90 1.70 1.90 v power supply currents i avdd33 56 60 56 60 56 60 ma i dvdd33 10 14 10 14 11 15 ma i cvdd18 18 22 18 22 18 22 ma i dvdd18 28 32 29 33 30 34 ma power dissipation f dac = 250 msps, f out = 20 mhz 300 345 300 345 305 350 mw dac outputs disabled 115 115 120 mw full device power-down 3 3 3 mw operating temperature ?40 +85 ?40 +85 ?40 +85 c
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 4 of 28 t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i fs = 20 ma, full-scale digital input, maximum sample rate, unless otherwise noted. the ad9745 is repeated in table 2 so the user can compare it with all other parts. table 2. ad9745, ad9746, and ad9747 ad9745 ad9746 ad9747 parameter min typ max min typ max min typ max unit resolution 12 14 16 bits accuracy differential nonlinearity (dnl) 0.13 0.5 2.0 lsb integral nonlinearity (inl) 0.25 1.0 4.0 lsb main dac outputs offset error 0.001 0.001 0.001 %fsr offset error temperature coefficient 0.1 0.1 0.1 ppm/c gain error 2.0 2.0 2.0 %fsr gain error temperature coefficient 100 100 100 ppm/c gain matching (dac1 to dac2) 1.0 1.0 1.0 %fsr full-scale output current 8.6 31.7 8.6 31.7 8.6 31.7 ma output compliance voltage ?1.0 +1.0 ?1.0 +1.0 ?1.0 +1.0 v output resistance 10 10 10 m auxiliary dac outputs resolution 10 10 10 bits full-scale output current ?2.0 +2.0 ?2.0 +2.0 ?2.0 +2.0 ma output compliance voltage rangesink current 0.8 1.6 0.8 1.6 0.8 1.6 v output compliance voltage rangesource current 0 1.6 0 1.6 0 1.6 v output resistance 1 1 1 m monotonicity 10 10 10 bits reference input/output output voltage 1.2 1.2 1.2 v output voltage temperature coefficient 10 10 10 ppm/c external input voltage range 1.15 1.3 1.15 1.3 1.15 1.3 v input or output resistance 5 5 5 k power supply voltages avdd33, dvdd33 3.13 3.47 3.13 3.47 3.13 3.47 v cvdd18, dvdd18 1.70 1.90 1.70 1.90 1.70 1.90 v power supply currents i avdd33 56 60 56 60 56 60 ma i dvdd33 11 15 12 16 12 16 ma i cvdd18 18 22 18 22 18 22 ma i dvdd18 30 34 31 35 32 36 ma power dissipation f dac = 250 msps, f out = 20 mhz 305 350 310 355 310 355 mw dac outputs disabled 120 125 125 mw full device power-down 3 3 3 mw operating temperature ?40 +85 ?40 +85 ?40 +85 c
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 5 of 28 ac specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i fs = 20 ma, full-scale digital input, maximum sample rate, unless otherwise noted. table 3. ad9741, AD9743, and ad9745 ad9741 AD9743 ad9745 parameter min typ max min typ max min typ max unit spurious free dynamic range (sfdr) f dac = 250 msps, f out = 20 mhz 70 80 82 dbc f dac = 250 msps, f out = 70 mhz 70 70 70 dbc f dac = 250 msps, f out = 180 mhz 1 64 64 66 dbc intermodulation distortion (imd) f dac = 250 msps, f out = 20 mhz 80 80 86 dbc f dac = 250 msps, f out = 70 mhz 80 80 80 dbc f dac = 250 msps, f out = 180 mhz 1 72 72 74 dbc crosstalk f dac = 250 msps, f out = 20 mhz 80 80 80 dbc f dac = 250 msps, f out = 70 mhz 80 80 80 dbc f dac = 250 msps, f out = 180 mhz 1 80 80 80 dbc adjacent channel leakage ratio (aclr) single carrier wcdma f dac = 245.76 msps, f out = 15.36 mhz 54 66 76 dbc f dac = 245.76 msps, f out = 61.44 mhz 54 66 76 dbc f dac = 245.76 msps, f out = 184.32 mhz 1 54 64 72 dbc noise spectral density (nsd) f dac = 245.76 msps, f out = 15.36 mhz ?132 ?144 ?155 dbm/hz f dac = 245.76 msps, f out = 61.44 mhz ?132 ?144 ?155 dbm/hz f dac = 245.76 msps, f out = 184.32 mhz 1 ?135 ?147 ?155 dbm/hz 1 mix mode.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 6 of 28 t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i fs = 20 ma, full-scale digital input, maximum sample rate, unless otherwise noted. the ad9745 is repeated in table 4 so the user can compare it with all other parts. table 4. ad9745, ad9746, and ad9747 ad9745 ad9746 ad9747 parameter min typ max min typ max min typ max unit spurious free dynamic range (sfdr) f dac = 250 msps, f out = 20 mhz 82 82 82 dbc f dac = 250 msps, f out = 70 mhz 70 70 70 dbc f dac = 250 msps, f out = 180 mhz 1 66 66 66 dbc intermodulation distortion (imd) f dac = 250 msps, f out = 20 mhz 86 86 86 dbc f dac = 250 msps, f out = 70 mhz 80 80 80 dbc f dac = 250 msps, f out = 180 mhz 1 74 74 74 dbc crosstalk f dac = 250 msps, f out = 20 mhz 80 80 80 dbc f dac = 250 msps, f out = 70 mhz 80 80 80 dbc f dac = 250 msps, f out = 180 mhz 1 80 80 80 dbc adjacent channel leakage ratio (aclr) single carrier wcdma f dac = 245.76 msps, f out = 15.36 mhz 76 78 82 dbc f dac = 245.76 msps, f out = 61.44 mhz 76 78 80 dbc f dac = 245.76 msps, f out = 184.32 mhz 1 72 74 74 dbc noise spectral density (nsd) f dac = 245.76 msps, f out = 15.36 mhz ?155 ?163 ?165 dbm/hz f dac = 245.76 msps, f out = 61.44 mhz ?155 ?160 ?162 dbm/hz f dac = 245.76 msps, f out = 184.32 mhz 1 ?155 ?158 ?160 dbm/hz 1 mix mode.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 7 of 28 digital and timing specifications t min to t max , avdd33 = 3.3 v, dvdd33 = 3.3 v, dvdd18 = 1.8 v, cvdd18 = 1.8 v, i fs = 20 ma, full-scale digital input, maximum sample rate, unless otherwise noted. table 5. ad9741/AD9743/ad9745/ad9746/ad9747 parameter min typ max unit dac clock inputs (clkp, clkn) differential peak-to-peak voltage 400 800 1600 mv single-ended peak-to-peak voltage 800 mv common-mode voltage 300 400 500 mv input current 1 a input frequency 250 mhz data clock output (dco) output voltage high 2.4 v output voltage low 0.4 v output current 10 ma dac clock to data clock output delay (t dco ) 2.0 2.2 2.8 ns data port inputs input voltage high 2.0 v input voltage low 0.8 v input current 1 a data to dac clock setup time (t dbs dual-port mode) 400 ps data to dac clock hold time (t dbh dual-port mode) 1200 ps dac clock to analog output data late ncy (dual-port mode) 7 cycles data or iqsel input to dac clock setup time (t dbs single-port mode) 400 ps data or iqsel input to dac clock hold time (t dbh single-port mode) 1200 ps dac clock to analog output data late ncy (single-port mode) 8 cycles serial peripheral interface sclk frequency (f sclk ) 40 mhz sclk pulse width high (t pwh ) 10 ns sclk pulse width low (t pwl ) 10 ns csb to sclk setup time (t s ) 1 ns csb to sclk hold time (t h ) 0 ns sdio to sclk setup time (t ds ) 1 ns sdio to sclk hold time (t dh ) 0 ns sclk to sdio/sdo data valid time (t dv ) 1 ns reset pulse width high 10 ns wake-up time and output latency from dac outputs disabled 200 s from full device power-down 1200 s dac clock to analog output latency (dual-port mode) 7 cycles dac clock to analog output latency (single-port mode) 8 cycles
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 8 of 28 absolute maximum ratings table 6. parameter with respect to rating avdd33, dvdd33 avss dvss cvss ?0.3 v to +3.6 v dvdd18, cvdd18 avss dvss cvss ?0.3 v to +1.98 v avss dvss cvss ?0.3 v to +0.3 v dvss avss cvss ?0.3 v to +0.3 v cvss avss dvss ?0.3 v to +0.3 v refio avss ?0.3 v to avdd33 + 0.3 v iout1p, iout1n, iout2p, iout2p, aux1p, aux1n, aux2p, aux2n avss ?1.0 v to avdd33 + 0.3 v p1d15 to p1d0, p2d15 to p2d0 dvss ?0.3 v to dvdd33 + 0.3 v clkp, clkn cvss ?0.3 v to cvdd18 + 0.3 v reset, csb, sclk, sdio, sdo dvss C0.3 v to dvdd33 + 0.3 v junction temperature 125c storage temperature ?65c to +150c thermal resistance thermal resistance tested using jedec standard 4-layer thermal test board with no airflow. table 7. package type ja unit cp-72-1 (exposed pad soldered to pcb) 25 c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 9 of 28 pin configurations and function descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cvdd18 cvss clkp clkn cvss cvdd18 dvss dvdd18 p1d7 p1d6 p1d5 p1d4 p1d3 p1d2 p1d1 p1d0 17 nc 18 nc 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 nc nc nc nc nc nc dco nc dvdd33 dvss iqsel nc p2d7 p2d6 p2d5 p2d4 35 p2d3 36 p2d2 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 fsadj reset csb sclk sdio sdo dvss dvdd18 nc nc nc nc nc nc nc nc p2d0 p2d1 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 avdd33 avdd33 avss iout1p iout1n avss aux1p aux1n avss aux2n aux2p avss iout2n iout2p avss avdd33 avdd33 refio nc = no connect 06569-006 pin 1 indicator ad9741 (top view) figure 2. ad9741 pin configuration table 8. ad 9741 pin function descriptions pin no. mnemonic description 1, 6 cvdd18 clock supply voltage (1.8 v). 2, 5 cvss clock supply common (0 v). 3 clkp differential dac clock input. 4 clkn complementary differential dac clock input. 7, 28, 48 dvss digital supply common (0 v). 8, 47 dvdd18 digital core supply voltage (1.8 v). 9 to 16 p1d<7:0> port 1 data bit inputs. 17 to 24, 26, 30, 39 to 46 nc no connect. 25 dco data clock output. use to clock data source. 27 dvdd33 digital i/o supply voltage (3.3 v). 29 iqsel i/q framing signal for single-port mode operation. 31 to 38 p2d<7:0> port 2 data bit inputs. 49 sdo serial peripheral interface data output. 50 sdio serial peripheral interface da ta input and optional data output. 51 sclk serial peripheral interface clock input. 52 csb serial peripheral interface chip select input. active low. 53 reset hardware reset. active high. 54 fsadj full-scale current output adjust. connect a 10 k resistor to avss. 55 refio reference input/output. connect a 0.1 f capacitor to avss. 56, 57, 71, 72 avdd33 analog supply voltage (3.3 v). 58, 61, 64, 67, 70 avss analog supply common (0 v). 59 iout2p dac2 current output true. sources full- scale current when input data bits are all 1. 60 iout2n dac2 current output complement. source s full-scale current when data bits are all 0. 62 aux2p auxiliary dac2 default current output pin. 63 aux2n auxiliary dac2 optional output pin. enable through spi. 65 aux1n auxiliary dac1 optional output pin. enable through spi. 66 aux1p auxiliary dac1 default current output pin. 68 iout1n complementary dac1 current output. source s full-scale current when data bits are all 0. 69 iout1p dac1 current output. sources full- scale current when data bits are all 1. epad avss exposed thermal pad. must be soldered to copper pour on top surface of pcb for mechanical stability and must be electrically tied to low impedance gnd plane for low noise performance.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 10 of 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cvdd18 cvss clkp clkn cvss cvdd18 dvss dvdd18 p1d9 p1d8 p1d7 p1d6 p1d5 p1d4 p1d3 p1d2 17 p1d1 18 p1d0 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 nc nc nc nc nc nc dco nc dvdd33 dvss iqsel nc p2d9 p2d8 p2d7 p2d6 35 p2d5 36 p2d4 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 fsadj reset csb sclk sdio sdo dvss dvdd18 nc nc nc nc nc nc p2d0 p2d1 p2d2 p2d3 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 avdd33 avdd33 avss iout1p iout1n avss aux1p aux1n avss aux2n aux2p avss iout2n iout2p avss avdd33 avdd33 refio nc = no connect 06569-005 pin 1 indicator AD9743 (top view) figure 3. AD9743 pin configuration table 9. ad 9743 pin function descriptions pin no. mnemonic description 1, 6 cvdd18 clock supply voltage (1.8 v). 2, 5 cvss clock supply common (0 v). 3 clkp differential dac clock input. 4 clkn complementary differential dac clock input. 7, 28, 48 dvss digital supply common (0 v). 8, 47 dvdd18 digital core supply voltage (1.8 v). 9 to 18 p1d<9:0> port 1 data bit inputs. 19 to 24, 26, 30, 41 to 46 nc no connect. 25 dco data clock output. use to clock data source. 27 dvdd33 digital i/o supply voltage (3.3 v). 29 iqsel i/q framing signal for single-port mode operation. 31 to 40 p2d<9:0> port 2 data bit inputs. 49 sdo serial peripheral interface data output. 50 sdio serial peripheral interface da ta input and optional data output. 51 sclk serial peripheral interface clock input. 52 csb serial peripheral interface chip select input. active low. 53 reset hardware reset. active high. 54 fsadj full-scale current output adjust. connect a 10 k resistor to avss. 55 refio reference input/output. connect a 0.1 f capacitor to avss. 56, 57, 71, 72 avdd33 analog supply voltage (3.3 v). 58, 61, 64, 67, 70 avss analog supply common (0 v). 59 iout2p dac2 current output true. sources full- scale current when input data bits are all 1. 60 iout2n dac2 current output complement. source s full-scale current when data bits are all 0. 62 aux2p auxiliary dac2 default current output pin. 63 aux2n auxiliary dac2 optional output pin. enable through spi. 65 aux1n auxiliary dac1 optional output pin. enable through spi. 66 aux1p auxiliary dac1 default current output pin. 68 iout1n complementary dac1 current output. sour ces full-scale current when data bits are all 0. 69 iout1p dac1 current output. sources full- scale current when data bits are all 1. epad avss exposed thermal pad. must be soldered to copp er pour on top surface of pcb for mechanical stability and must be electrically tied to lo w impedance gnd plane for low noise performance.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 11 of 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cvdd18 cvss clkp clkn cvss cvdd18 dvss dvdd18 p1d11 p1d10 p1d9 p1d8 p1d7 p1d6 p1d5 p1d4 17 p1d3 18 p1d2 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 p1d1 p1d0 nc nc nc nc dco nc dvdd33 dvss iqsel nc p2d11 p2d10 p2d9 p2d8 35 p2d7 36 p2d6 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 fsadj reset csb sclk sdio sdo dvss dvdd18 nc nc nc nc p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 avdd33 avdd33 avss iout1p iout1n avss aux1p aux1n avss aux2n aux2p avss iout2n iout2p avss avdd33 avdd33 refio nc = no connect 06569-004 pin 1 indicator ad9745 (top view) figure 4. ad9745 pin configuration table 10. ad9745 pin function descriptions pin no. mnemonic description 1, 6 cvdd18 clock supply voltage (1.8 v). 2, 5 cvss clock supply common (0 v). 3 clkp differential dac clock input. 4 clkn complementary differential dac clock input. 7, 28, 48 dvss digital supply common (0 v). 8, 47 dvdd18 digital core supply voltage (1.8 v). 9 to 20 p1d<11:0> port 1 data bit inputs. 21 to 24, 26, 30, 43 to 46 nc no connect. 25 dco data clock output. use to clock data source. 27 dvdd33 digital i/o supply voltage (3.3 v). 29 iqsel i/q framing signal for single-port mode operation. 31 to 42 p2d<11:0> port 2 data bit inputs. 49 sdo serial peripheral interface data output. 50 sdio serial peripheral interface da ta input and optional data output. 51 sclk serial peripheral interface clock input. 52 csb serial peripheral interface chip select input. active low. 53 reset hardware reset. active high. 54 fsadj full-scale current output adjust. connect 10 k resistor to avss. 55 refio reference input/output. connect a 0.1 f capacitor to avss. 56, 57, 71, 72 avdd33 analog supply voltage (3.3 v). 58, 61, 64, 67, 70 avss analog supply common (0 v). 59 iout2p dac2 current output true. sources full- scale current when input data bits are all 1. 60 iout2n dac2 current output complement. source s full-scale current when data bits are all 0. 62 aux2p auxiliary dac2 default current output pin. 63 aux2n auxiliary dac2 optional output pin. enable through spi. 65 aux1n auxiliary dac1 optional output pin. enable through spi. 66 aux1p auxiliary dac1 default current output pin. 68 iout1n complementary dac1 current output. sour ces full-scale current when data bits are all 0. 69 iout1p dac1 current output. sources full- scale current when data bits are all 1. epad avss exposed thermal pad. must be soldered to copp er pour on top surface of pcb for mechanical stability and must be electrically tied to lo w impedance gnd plane for low noise performance.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 12 of 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cvdd18 cvss clkp clkn cvss cvdd18 dvss dvdd18 p1d13 p1d12 p1d11 p1d10 p1d9 p1d8 p1d7 p1d6 17 p1d5 18 p1d4 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 p1d3 p1d2 p1d1 p1d0 nc nc dco nc dvdd33 dvss iqsel nc p2d13 p2d12 p2d11 p2d10 35 p2d9 36 p2d8 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 fsadj reset csb sclk sdio sdo dvss dvdd18 nc nc p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 p2d6 p2d7 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 avdd33 avdd33 avss iout1p iout1n avss aux1p aux1n avss aux2n aux2p avss iout2n iout2p avss avdd33 avdd33 refio nc = no connect 06569-003 pin 1 indicator ad9746 (top view) figure 5. ad9746 pin configuration table 11. ad9746 pin function descriptions pin no. mnemonic description 1, 6 cvdd18 clock supply voltage (1.8 v). 2, 5 cvss clock supply common (0 v). 3 clkp differential dac clock input. 4 clkn complementary differential dac clock input. 7, 28, 48 dvss digital supply common (0 v). 8, 47 dvdd18 digital core supply voltage (1.8 v). 9 to 22 p1d<13:0> port 1 data bit inputs. 23, 24, 26, 30, 45, 46 nc no connect. 25 dco data clock output. use to clock data source. 27 dvdd33 digital i/o supply voltage (3.3 v). 29 iqsel i/q framing signal for single-port mode operation. 31 to 44 p2d<13:0> port 2 data bit inputs. 49 sdo serial peripheral interface data output. 50 sdio serial peripheral interface da ta input and optional data output. 51 sclk serial peripheral interface clock input. 52 csb serial peripheral interface chip select input. active low. 53 reset hardware reset. active high. 54 fsadj full-scale current output adjust. connect a 10 k resistor to avss. 55 refio reference input/output. connect a 0.1 f capacitor to avss. 56, 57, 71, 72 avdd33 analog supply voltage (3.3 v). 58, 61, 64, 67, 70 avss analog supply common (0 v). 59 iout2p dac2 current output true. sources full- scale current when input data bits are all 1. 60 iout2n dac2 current output complement. source s full-scale current when data bits are all 0. 62 aux2p auxiliary dac2 default current output pin. 63 aux2n auxiliary dac2 optional output pin. enable through spi. 65 aux1n auxiliary dac1 optional output pin. enable through spi. 66 aux1p auxiliary dac1 default current output pin. 68 iout1n complementary dac1 current output. sour ces full-scale current when data bits are all 0. 69 iout1p dac1 current output. sources full- scale current when data bits are all 1. epad avss exposed thermal pad. must be soldered to copper pour on top surface of pcb for mechanical stability and must be electrically tied to low impedance gnd plane for low noise performance.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 13 of 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cvdd18 cvss clkp clkn cvss cvdd18 dvss dvdd18 p1d15 p1d14 p1d13 p1d12 p1d11 p1d10 p1d9 p1d8 17 p1d7 18 p1d6 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 p1d5 p1d4 p1d3 p1d2 p1d1 p1d0 dco nc dvdd33 dvss iqsel nc p2d15 p2d14 p2d13 p2d12 35 p2d11 36 p2d10 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 fsadj reset csb sclk sdio sdo dvss dvdd18 p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 p2d6 p2d7 p2d8 p2d9 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 avdd33 avdd33 avss iout1p iout1n avss aux1p aux1n avss aux2n aux2p avss iout2n iout2p avss avdd33 avdd33 refio nc = no connect 06569-002 pin 1 indicator ad9747 (top view) figure 6. ad9747 pin configuration table 12. ad9747 pin function descriptions pin no. mnemonic description 1, 6 cvdd18 clock supply voltage (1.8 v). 2, 5 cvss clock supply common (0 v). 3 clkp differential dac clock input. 4 clkn complementary differential dac clock input. 7, 28, 48 dvss digital supply common (0 v). 8, 47 dvdd18 digital core supply voltage (1.8 v). 9 to 24 p1d<15:0> port 1 data bit inputs. 25 dco data clock output. use to clock data source. 26, 30 nc no connect. 27 dvdd33 digital i/o supply voltage (3.3 v). 29 iqsel i/q framing signal for single-port mode operation. 31 to 46 p2d<15:0> port 2 data bit inputs. 49 sdo serial peripheral interface data output. 50 sdio serial peripheral interface da ta input and optional data output. 51 sclk serial peripheral interface clock input. 52 csb serial peripheral interface chip select input. active low. 53 reset hardware reset. active high. 54 fsadj full-scale current output adjust. connect a 10 k resistor to avss. 55 refio reference input/output. connect a 0.1 f capacitor to avss. 56, 57, 71, 72 avdd33 analog supply voltage (3.3 v). 58, 61, 64, 67, 70 avss analog supply common (0 v). 59 iout2p dac2 current output. sources full-sc ale current when input data bits are all 1. 60 iout2n complementary dac2 current output. sour ces full-scale current when data bits are all 0. 62 aux2p auxiliary dac2 default current output pin. 63 aux2n auxiliary dac2 optional output pin. enable through spi. 65 aux1n auxiliary dac1 optional output pin. enable through spi. 66 aux1p auxiliary dac1 default current output pin. 68 iout1n complementary dac1 current output. sour ces full-scale current when data bits are all 0. 69 iout1p dac1 current output. sources full- scale current when data bits are all 1. epad avss exposed thermal pad. must be soldered to copp er pour on top surface of pcb for mechanical stability and must be electrically tied to lo w impedance gnd plane for low noise performance.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 14 of 28 typical performance characteristics 40 50 60 70 80 90 100 0 20406080100120 250msps 125msps 06569-007 f out (mhz) sfdr (dbc) figure 7. ad9747 sfdr vs. f out , normal mode 150 175 200 225 40 50 60 70 80 90 100 125 250 06569-008 f out (mhz) sfdr (dbc) figure 8. ad9747 sfdr vs. f out , mix mode, 250 msps 60 65 70 75 80 85 90 50 100 150 200 0 250 06569-009 f out (mhz) aclr (dbc) normal mode mix mode figure 9. ad9747 aclr vs. f out , single carrier wcdma, 245.76 msps 40 50 60 70 80 90 100 0 20406080100120 250msps 06569-010 f out (mhz) imd (dbc) 125msps figure 10. ad9747 imd vs. f out , normal mode 150 175 200 225 40 50 60 70 80 90 100 125 250 06569-011 f out (mhz) imd (dbc) figure 11. ad9747 imd vs. f out , mix mode, 250 msps ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ? 152 50 100 150 200 02 06569-012 f out (mhz) nsd (dbm/hz) 5 0 normal mode mix mode figure 12. ad9747 nsd vs. f out , single carrier wcdma, 245.76 msps
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 15 of 28 30mafs 40 50 60 70 80 90 100 0 20 40 60 80 100 120 06569-036 f out (mhz) sfdr (dbc) 10mafs 20mafs figure 13. ad9747 sfdr vs. analog output, 250 msps ?3dbfs 40 50 60 70 80 90 100 0 20 40 60 80 100 120 06569-037 f in (mhz) sfdr (dbc) ?6dbfs 0dbfs figure 14. ad9747 sfdr vs. digital input, 250 msps 60 65 70 75 80 85 90 10 20 30 40 50 60 70 80 90 100 110 range of possible sfdr performance is dependent on input data timing relative to the dac clock. see input data timing section. 06569-038 f out (mhz) sfdr (dbc) figure 15. ad9747 sfdr vs. f out over input data timing 10mafs 20mafs 30mafs 40 50 60 70 80 90 100 0 20406080100120 06569-039 f out (mhz) imd (dbc) figure 16. ad9747 imd vs. analog output, 250 msps 0dbfs ?3dbfs 40 50 60 70 80 90 100 0 20406080100120 06569-040 f in (mhz) imd (dbc) ?6dbfs figure 17. ad9747 imd vs. digital input, 250 msps f out (mhz) 60 65 70 75 80 85 90 20 30 40 50 60 70 80 90 100 110 10 06569-041 imd (dbc) range of imd performance is essentially independent of input data timing relative to the dac clock. see input data timing section. figure 18. ad9747 imd vs. f out over input data timing
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 16 of 28 ?5 ?4 ?3 ?2 ?1 0 1 25 75 125 175 225 50 100 150 200 0 250 06569-042 f out (mhz) a out (dbm) normal mode mix mode ?165 ?160 ?155 ?150 ?145 ?140 ?135 ? 130 ad9747 ad9746 ad9745 AD9743 ad9741 06569-044 nsd (dbm/hz) figure 19. nominal power in the fundamental, i fs = 20 ma figure 21. nsd vs. bit resolution, single carrier wcdma, 245.76 msps, f carrier f carrier = 61.44 mhz 50 55 60 65 70 75 80 85 ad9747 ad9746 ad9745 AD9743 ad9741 06569-043 aclr (dbc) figure 20. aclr vs. bit resolution, single carrier wcdma, 245.76 msps, f carrier = 61.44 mhz
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 17 of 28 terminology integral nonlinearity (inl) the maximum deviation of the actual analog output from the ideal output, as determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) a measure of the maximum deviation in analog output associated with any single value change in the digital input code relative to an ideal lsb. monotonicity a dac is monotonic if the analog output increases or remains constant in response to an increase in the digital input. offset error the deviation of the output current from the ideal zero-scale current. for differential outputs, 0 ma is expected at i outp when all inputs are low, and 0 ma is expected at i outn when all inputs are high. gain error the deviation of the output current from the ideal full-scale current. actual full-scale output current is determined by subtracting the output (when all inputs are low) from the output (when all inputs are high). output compliance range the range of allowable voltage seen by the analog output of a current output dac. operation beyond the compliance limits may cause output stage saturation and/or a breakdown resulting in nonlinear performance. temp er atu re d r i f t temperature drift is specified as the maximum change in a parameter from ambient temperature (25c) to either t min or t max and is typically reported as ppm/c. spurious-free dynamic range (sfdr) the difference in decibels between the peak amplitude of a test tone and the peak amplitude of the largest spurious signal over the specified bandwidth. intermodulation distortion (imd) the difference in decibels between the maximum peak ampli- tude of two test tones and the maximum peak amplitude of the distortion products created from the sum or difference of integer multiples of the test tones. adjacent channel leakage ratio (aclr) the ratio between the measured power of a wideband signal within a channel relative to the measured power in an empty adjacent channel. noise spectral density (nsd) the measured noise power over a 1 hz bandwidth seen at the analog output.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 18 of 28 theory of operation the ad9741/AD9743/ad9745/ad9746/ad9747 combine many features to make them very attractive for wired and wireless communications systems. the dual dac architecture facilitates easy interfacing to common quadrature modulators when designing single sideband transmitters. in addition, the speed and performance of the devices allow wider bandwidths and more carriers to be synthesized than in previously available products. all features and options are software programmable through the spi port. serial peripheral interface ad9747 spi port sdo sdio sclk csb 0 6569-013 figure 22. spi port the spi port is a flexible, synchronous serial communications port allowing easy interfacing to many industry-standard microcontrollers and microprocessors. the port is compatible with most synchronous transfer formats including both the motorola spi and intel ? ssr protocols. the interface allows read and write access to all registers that configure the ad9741/AD9743/ad9745/ad9746/ad9747. single or multiple byte transfers are supported as well as msb- first or lsb-first transfer formats. serial data input/output can be accomplished through a single bidirectional pin (sdio) or through two unidirectional pins (sdio/sdo). the serial port configuration is controlled by register 0x00, bits<7:6>. it is important to note that any change made to the serial port configuration occurs immediately upon writing to the last bit of this byte. therefore, it is possible with a multibyte transfer to write to this register and change the configuration in the middle of a communication cycle. care must be taken to compensate for the new configuration within the remaining bytes of the current communication cycle. use of a single-byte transfer when changing the serial port configuration is recommended to prevent unexpected device behavior. general operation of the serial interface there are two phases to any communication cycle with the ad9741/AD9743/ad9745/ad9746/ad9747: phase 1 and phase 2. phase 1 is the instruction cycle, which writes an instruction byte into the device. this byte provides the serial port controller with information regarding phase 2 of the communication cycle: the data transfer cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and a reference register address for the first byte of the data transfer. a logic high on the csb pin followed by a logic low resets the spi port to its initial state and defines the start of the instruction cycle. from this point, the next eight rising sclk edges define the eight bits of the instruction byte for the current communication cycle. the remaining sclk edges are for phase 2 of the communication cycle, which is the data transfer between the serial port control- ler and the system controller. phase 2 can be a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. using multibyte transfers is usually preferred although single-byte data transfers are useful to reduce cpu overhead or when only a single register access is required. all serial port data is transferred to and from the device in syn- chronization with the sclk pin. input data is always latched on the rising edge of sclk whereas output data is always valid after the falling edge of sclk. register contents change imme- diately upon writing to the last bit of each transfer byte. when synchronization is lost, the device has the ability to asynchronously terminate an i/o operation whenever the csb pin is taken to logic high. any unwritten register content data is lost if the i/o operation is aborted. taking csb low then resets the serial port controller and restarts the communication cycle. instruction byte the instruction byte contains the information shown in the following bit map. msb lsb b7 b6 b5 b4 b3 b2 b1 b0 r/w n1 n0 a4 a3 a2 a1 a0 bit 7, r/w, determines whether a read or a write data transfer occurs after the instruction byte write. logic high indicates a read operation. logic 0 indicates a write operation. bits<6:5>, n1 and n0, determine the number of bytes to be transferred during the data transfer cycle. the bits decode as shown in table 13 . table 13. byte transfer count n1 n0 description 0 0 transfer one byte 0 1 transfer two bytes 1 0 transfer three bytes 1 1 transfer four bytes bits<4:0>, a4, a3, a2, a1, and a0, determine which register is accessed during the data transfer of the communications cycle. for multibyte transfers, this address is a starting or ending address depending on the current data transfer mode. for msb- first format, the specified address is an ending address or the most significant address in the current cycle. remaining register addresses for multiple byte data transfers are generated
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 19 of 28 internally by the serial port controller by decrementing from the specified address. for lsb-first format, the specified address is a beginning address or the least significant address in the current cycle. remaining register addresses for multiple byte data transfers are generated internally by the serial port controller by incrementing from the specified address. msb/lsb transfers the serial port can support both msb-first and lsb-first data formats. this functionality is controlled by register 0x00, bit 6. the default is logic 0, which is msb-first format. when using msb-first format (lsbfirst = 0), the instruction and data bit must be written from msb to lsb. multibyte data transfers in msb-first format start with an instruction byte that includes the register address of the most significant data byte. subsequent data bytes are loaded into sequentially lower address locations. in msb-first mode, the serial port internal address generator decrements for each byte of the multibyte data transfer. when using lsb-first format (lsbfirst = 1), the instruction and data bit must be written from lsb to msb. multibyte data transfers in lsb-first format start with an instruction byte that includes the register address of the least significant data byte. subsequent data bytes are loaded into sequentially higher address locations. in lsb-first mode, the serial port internal address generator increments for each byte of the multibyte data transfer. use of a single-byte transfer when changing the serial port data format is recommended to prevent unexpected device behavior. serial interface port pin descriptions chip select bar (csb) active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communication lines. csb must stay low during the entire communication cycle. incomplete data transfers are aborted anytime the csb pin goes high. sdo and sdio pins go to a high impedance state when this input is high. serial clock (sclk) the serial clock pin is used to synchronize data to and from the device and to run the internal state machines. the maximum frequency of sclk is 40 mhz. all data input is registered on the rising edge of sclk. all data is driven out on the falling edge of sclk. serial data i/o (sdio) data is always written into the device on this pin. however, sdio can also function as a bidirectional data output line. the configuration of this pin is controlled by register 0x00, bit 7. the default is logic 0, which configures the sdio pin as unidirectional. serial data out (sdo) data is read from this pin for protocols that use separate lines for transmitting and receiving data. the configuration of this pin is controlled by register 0x00, bit 7. if this bit is set to a logic 1, the sdo pin does not output data and is set to a high impedance state. r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 d7 d6 n d5 n d0 0 d1 0 d2 0 d3 0 instruction cycle data transfer cycle csb sclk sdio sdo 06569-014 figure 23. serial register interfacemsb first a0 a1 a2 a3 a4 n0 n1 r/w d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n d0 0 d1 0 d2 0 d7 n d6 n d5 n d4 n instruction cycle data transfer cycle csb sclk sdio sdo 0 6569-015 figure 24. serial register interface timinglsb first instruction bit 6 instruction bit 7 csb sclk sdio t s t ds t dh t pwh t pwl f sclk ?1 06569-016 figure 25. timing diagram for spi register write data bit n ? 1 data bit n csb sclk sdio sdo t dv 06569-017 figure 26. timing diagram for spi register read
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 20 of 28 spi register map reading any register returns previously written values for all defined register bits, unless otherwise noted. change serial por t configu- ration or execute software reset in single byte instruction only to avoid unexpected device behavior. table 14. register name address default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 spi control 0x00 0x00 sdiodir lsbfirst swreset data control 0x02 0x00 dattype oneport invdco power down 0x03 0x00 pd_dco pd_aux2 pd_aux1 pd_bias pc_clk pd_dac2 pd_dac1 dac mode select 0x0a 0x00 dac1mod<1:0> dac2mod<1:0> dac1 gain lsb 0x0b 0xf9 dac1fsc<7:0> dac1 gain msb 0x0c 0x01 dac1fsc<9:8> aux dac1 lsb 0x0d 0x00 auxdac1<7:0> aux dac1 msb 0x0e 0x00 aux1pin aux1dir auxdac1<9:8> dac2 gain lsb 0x0f 0xf9 dac2fsc<7:0> dac2 gain msb 0x10 0x01 dac2fsc<9:8> aux dac2 lsb 0x11 0x00 auxdac2<7:0> aux dac2 msb 0x12 0x00 aux2pin aux2dir auxdac2<9:8>
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 21 of 28 spi register descriptions table 15. register address bit name description 7 sdiodir 0, operate spi in 4-wire mode, sdio pin operates as an input only 1, operate spi in 3-wire mode, sdio pin operates as a bidirectional i/o line 6 lsbfirst 0, lsbfirst off, spi serial data mode is msb to lsb 1, lsbfirst on, spi serial data mode is lsb to msb 5 swreset 0, resume normal operation following software reset spi control 0x00 1, software reset; loads default values to all registers (except register 0x00) 7 dattype 0, dac input data is twos complement binary format 1, dac input data is unsigned binary format 6 oneport 0, normal two port input mode 1, optional single port input mode, interleaved data received on port 1 only data control 0x02 4 invdco 1, inverts data clock output signal 7 pd_dco 1, power down data clock output 5 pd_aux2 1, power down aux2 dac 4 pd_aux1 1, power down aux1 dac 3 pd_bias 1, power down reference voltage bias circuit 2 pd_clk 1, power down dac clock input circuit 1 pd_dac2 1, power down dac2 analog output power down 0x03 0 pd_dac1 1, power down dac1 analog output 3:2 dac1mod<1:0> 00, selects normal mode, dac1 01, selects mix mode, dac1 10, selects return-to-zero mode, dac1 1:0 dac2mod<1:0> 00, selects normal mode, dac2 01, selects mix mode, dac2 dac mode select 0x0a 10, selects return-to-zero mode, dac2 0x0b 7:0 dac1fsc<7:0> dac1 full-scale 10-bit adjustment word 1:0 dac1fsc<9:8> 0x03ff, sets full-scale current to the maximum value of 31.66 ma 0x01f9, sets full-scale curren t to the nominal value of 20.0 ma dac1 gain 0x0c 0x0000, sets full-scale curren t to the minimum value of 8.64 ma 0x0d 7:0 auxdac1<7:0> auxiliary dac1 10-bit output current adjustment word 1:0 auxdac1<9:8> 0x03ff, sets output current magnitude to 2.0 ma 0x0200, sets output current magnitude to 1.0 ma 0x0000, sets output current magnitude to 0.0 ma 7 aux1pin 0, aux1p output pin is active 1, aux1n output pin is active 6 aux1dir 0, configures aux1 dac output to source current aux dac1 0x0e 1, configures aux1 dac output to sink current 0x0f 7:0 dac2fsc<7:0> dac2 full-scale 10-bit adjustment word 1:0 dac2fsc<9:8> 0x03ff, sets full-scale current to the maximum value of 31.66 ma 0x01f9, sets full-scale curren t to the nominal value of 20.0 ma dac2 gain 0x10 0x0000, sets full-scale curren t to the minimum value of 8.64 ma 0x11 7:0 auxdac2<7:0> auxiliary dac2 10-bit output current adjustment word 0x12 1:0 auxdac2<9:8> 0x03ff, sets output current magnitude to 2.0 ma 0x0200, sets output current to 1.0 ma 0x0000, sets output current to 0.0 ma 7 aux2pin 0, aux2p output pin is active 1, aux2n output pin is active 6 aux2dir 0, configures aux2 dac output to source current aux dac2 1, configures aux2 dac output to sink current
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 22 of 28 digital inputs and outputs the ad9741/AD9743/ad9745/ad9746/ad9747 can operate in two data input modes: dual-port mode and single-port mode. for the default dual-port mode (oneport = 0), each dac receives data from a dedicated input port. in single-port mode (oneport = 1), however, both dacs receive data from port 1. in single-port mode, dac1 and dac2 data is interleaved and the iqsel input is used to steer data to the correct dac. in single-port mode, when the iqsel input is high, port 1 data is delivered to dac1 and when iqsel is low, port 1 data is delivered to dac2. the iqsel input should always coincide and be time-aligned with the other data bus signals. in single- port mode, minimum setup and hold times apply to the iqsel input as well as to the input data signals. in dual-port mode, the iqsel input is ignored. in dual-port mode, the data must be delivered at the sample rate (up to 250 msps). in single-port mode, data must be delivered at twice the sample rate. because the data inputs function only up to 250 msps, it is only practical to operate the dac clock at up to 125 mhz in single-port mode. in both dual-port and single-port modes, a data clock output (dco) signal is available as a fixed time base with which to stimulate data from an fpga. this output signal always operates at the sample rate. it may be inverted by asserting the invdco bit. input data timing with most dacs, signal-to-noise ratio (snr) is a function of the relationship between the position of the clock edges and the point in time at which the input data changes. the ad9741/ AD9743/ad9745/ad9746/ad9747 are rising edge triggered and thus exhibit greater snr sensitivity when the data tran- sition is close to this edge. the specified minimum setup and hold times define a window of time, within each data period, where the data is sampled correctly. generally, users should position data to arrive relative to the dac clock and well beyond the minimum setup and minimum hold times. this becomes increasingly more important at increasingly higher sample rates. dual-port mode timing the timing diagram for the dual-port mode is shown in figure 27. clkp/clkn dco p1d<15:0> p2d<15:0> t dco t dbh t dbs 06569-018 i1 i2 i3 i4 q1 q2 q3 q4 figure 27. data interface timing, dual-port mode in figure 27, data samples for dac1 are labeled ix and data samples for dac2 are labeled qx. note that the differential dac clock input is shown in a logical sense (clkp/clkn). the data clock output is labeled dco. setup and hold times are referenced to the positive transition of the dac clock. data should arrive at the input pins such that the minimum setup and hold times are met. note that the data clock output has a fixed time delay from the dac clock and may be a more convenient signal to use to confirm timing. single-port mode timing the single-port mode timing diagram is shown in figure 28. 06569-019 clkp/clkn dco p1d<15:0> iqsel t dbs t dbh t dco i1 q1 i2 q2 figure 28. data interface timing, single-port mode in single-port mode, data for both dacs is received on the port 1 input bus. ix and qx data samples are interleaved and arrive twice as fast as in dual-port mode. accompanying the data is the iqsel input signal, which steers incoming data to its respective dac. when iqsel is high, data is steered to dac1 and when iqsel is low, data is steered to dac2. iqsel should coincide as well as be time-aligned with incoming data. spi port, reset, and pin mode in general, when the ad9741/AD9743/ad9745/ad9746/ ad9747 are powered up, an active high pulse applied to the reset pin should follow. this insures the default state of all control register bits. in addition, once the reset pin goes low, the spi port can be activated, so csb should be held high. for applications without a controller, the ad9741/AD9743/ ad9745/ad9746/ad9747 also support pin mode operation, which allows some functional options to be pin, selected with- out the use of the spi port. pin mode is enabled anytime the reset pin is held high. in pin mode, the four spi port pins take on secondary functions, as shown in table 16. table 16. spi pin functions (pin mode) pin name pin mode description sclk oneport (register 0x02, bit 6), bit value (1/0) equals pin state (high/low) sdio dattype (register 0x02, bit 7), bit value (1/0) equals pin state (high/low) csb enable mix mode, if csb is high, register 0x0a is set to 0x05 putting both dac1 and dac2 into mix mode sdo enable full power-down, if sdo is high, register 0x03 is set to 0xff
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 23 of 28 in pin mode, all register bits are reset to their default values with the exception of those that are controlled by the spi pins. note also that the reset pin should be allowed to float and must be pulled low. connect an external 10 k resistor to dvss. this avoids unexpected behavior in noisy environments. driving the dac clock input the dac clock input requires a low jitter drive signal. it is a pmos differential pair powered from the cvdd18 supply. each pin can safely swing up to 800 mv p-p at a common- mode voltage of about 400 mv. though these levels are not directly lvds-compatible, clkp and clkn can be driven by an ac-coupled, dc-offset lvds signal, as shown in figure 29 . lvds_p_in clkp 50? 50? 0.1 f 0.1f lvds_n_in clkn v cm = 400mv 06569-021 figure 29. lvds dac clock drive circuit using a cmos or ttl clock is also acceptable for lower sample rates. it can be routed through an lvds translator and then ac-coupled as described previously, or alternatively, it can be transformer-coupled and clamped, as shown in figure 30 . 50? 50? t tl or cmos clk input clkp clkn v cm = 400mv bav99zxct high speed dual diode 0.1 f 06569-022 figure 30. ttl or cmos dac clock drive circuit if a sine wave signal is available, it can be transformer-coupled directly to the dac clock inputs, as shown in figure 31 . 50 ? sine wave input clkp clkn v cm = 400mv 06569-034 figure 31. sine wave dac clock drive circuit the 400 mv common-mode bias voltage can be derived from the cvdd18 supply through a simple divider network, as shown in figure 32 . 0.1f 1nf v cm = 400mv cvdd18 cvss 1k ? 2 87? 06569-023 figure 32. dac clock vcm circuit it is important to use cvdd18 and cvss for any clock bias circuit as noise that is coupled onto the clock from another power supply is multiplied by the dac input signal and degrades performance. full-scale current generation the full-scale currents on dac1 and dac2 are functions of the current drawn through an external resistor connected to the fsadj pin (pin 54). the required value for this resistor is 10 k. an internal amplifier sets the current through the resistor to force a voltage equal to the band gap voltage of 1.2 v. this develops a reference current in the resistor of 120 a. current scaling 1.2v bandgap dac1 gain dac2 gain ad9747 dac1 dac2 dac full scale reference current refio fsadj 0 .1 f 10k ? 06569-024 figure 33. reference circuitry refio (pin 55) should be bypassed to ground with a 0.1 f capacitor. the band gap voltage is present on this pin and can be buffered for use in external circuitry. the typical output impedance is near 5 k. if desired, an external reference can be connected to refio to overdrive the internal reference. internal current mirrors provide a means for adjusting the dac full-scale currents. the gain for dac1 and dac2 can be adjusted independently by writing to the dac1fsc<9:0> and dac2fsc<9:0> register bits. the default value of 0x01f9 for the dac gain registers gives an i fs of 20 ma, where i fs equals ? ? ? ? ? ? ? ? ? ? ? ? += fscdac i fs n 16 3 72 10,000 v 1.2 the full-scale output current range is 8.6 ma to 31.7 ma for register values 0x000 to 0x3ff. 06569-025 35 30 25 20 15 10 5 i fs (ma) 0 256 512 768 1024 dac gain code figure 34. i fs vs. dac gain code
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 24 of 28 dac transfer function each dac output of the ad9741/AD9743/ad9745/ad9746/ ad9747 drives complementary current outputs i outp and i outn . i outp provides a near full-scale current output (i fs ) when all bits are high. for example, dac code = 2 n ? 1 where: n = 8-/10-/12-/14-/16-bits (for ad9741/AD9743/ad9745/ ad9746/ad9747 respectively), and i outn provides no current. the current output appearing at i outp and i outn is a function of both the input code and i fs and can be expressed as i outp = ( dac data /2 n ) i fs (1) i outn = ((2 n ? 1) ? dac data )/2 n i fs (2) where dac data = 0 to 2 n ? 1 (decimal representation). the two current outputs typically drive a resistive load directly or via a transformer. if dc coupling is required, i outp and i outn should be connected to matching resistive loads (r load ) that are tied to analog common (avss). the single-ended voltage output appearing at the i outp and i outn pins is v outp = i outp r load (3) v outn = i outn r load (4) note that to achieve the maximum output compliance of 1 v at the nominal 20 ma output current, r load must be set to 50 . also note that the full-scale value of v outp and v outn should not exceed the specified output compliance range to maintain specified distortion and linearity performance. there are two distinct advantages to operating the ad9741/ AD9743/ad9745/ad9746/ad9747 differentially. first, differ- ential operation helps cancel common-mode error sources associated with i outp and i outn , such as noise, distortion, and dc offsets. second, the differential code dependent current and subsequent output voltage (v diff ) is twice the value of the single-ended voltage output (v outp or v outn ), providing 2 signal power to the load. v diff = ( i outp C i outn ) r load (5) analog modes of operation the ad9741/AD9743/ad9745/ad9746/ad9747 utilize a proprietary quad-switch architecture that lowers the distortion of the dac output by eliminating a code dependent glitch that occurs with conventional dual-switch architectures. but whereas this architecture eliminates the code dependent glitches, it creates a constant glitch at a rate of 2 f dac . for communications systems and other applications requiring good frequency domain performance, this is seldom problematic. the quad-switch architecture also supports two additional modes of operation; mix mode and return-to-zero (rz) mode. the waveforms of these two modes are shown in figure 35. in mix mode, the output is inverted every other half clock cycle. this effectively chops the dac output at the sample rate. this chopping has the effect of frequency shifting the sinc roll-off from dc to f dac . additionally, there is a second subtle effect on the output spectrum. the shifted spectrum is shaped by a second sinc function with a first null at 2 f dac . the reason for this shaping is that the data is not continuously varying at twice the clock rate, but is simply repeated. in rz mode, the output is set to midscale on every other half clock cycle. the output is similar to the dac output in normal mode except that the output pulses are half the width and half the area. because the output pulses have half the width, the sinc function is scaled in frequency by 2 and has a first null at 2 f dac . because the area of the pulses is half that of the pulses in normal mode, the output power is half the normal mode output power. d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 10 input data dac clk 4-switch dac output ( f s mix mode) 4-switch dac output (return to zero mode) 0 6569-026 t t figure 35. mix mode and rz mode dac waveforms the functions that shape the output spectrums for normal mode, mix mode, and rz mode, are shown in figure 36. switching between the modes reshapes the sinc roll off inherent at the dac output. this ability to change modes in the ad9741/ AD9743/ad9745/d9746/ad9747 makes the parts suitable for direct if applications. the user can place a carrier anywhere in the first three nyquist zones depending on the operating mode selected. the performance and maximum amplitude in all three zones are impacted by this sinc roll off depending on where the carrier is placed, as shown in figure 36.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 25 of 28 0 ?10 ?20 ?30 ?40 t(f) (db) 0.5 1.5 2 f s normal rz mix 06569-027 figure 36. transfer function for each analog operating mode auxiliary dacs two auxiliary dacs are provided on the ad9741/AD9743/ ad9745/ad9746/ad9747. a functional diagram is shown in figure 37 . the auxiliary dacs are current output devices with two output pins, auxp and auxn. the active pin can be programmed to either source or sink current. when either sinking or sourcing, the full-scale current magnitude is 2 ma. the available compliance range at the auxiliary dac outputs depends on whether the output is configured to a sink or source current. when sourcing current, the compliance voltage is 0 v to 1.6 v, but when sinking current, the output compliance voltage reduces to 0.8 v to 1.6 v. either output can be used, but only one output of the auxiliary dac (p or n) is active at any time. the inactive pin is always in a high impedance state (>100 k). 06569-035 v bias auxp auxn sink or source positive or negative 0m a to 2ma 0ma to 2ma figure 37. auxiliary dac functional diagram in a single side band transmitter application, the combination of the input referred dc offset voltage of the quadrature modulator and the dac output offset voltage can result in local oscillator (lo) feedthrough at the modulator output, which degrades system performance. the auxiliary dacs can be used to remove the dc offset and the resulting lo feedthrough. the circuit configuration for using the auxiliary dacs for performing dc offset correction depends on the details of the dac and modulator interface. an example of a dc-coupled configuration with low-pass filtering is outlined in the power dissipation section. ad9747 aux dac1 or dac2 ad9747 dac1 or dac2 25? to 50 ? quad mod i or q inputs quadrature modulator v+ 25? to 50 ? 06569-029 optional passive filtering figure 38. dac dc coupled to quadratu re modulator with passive dc shift power dissipation figure 39 shows the power dissipation and current draw of the ad9741/AD9743/ad9745/ad9746/ad9747. it shows that the devices have a quiescent power dissipation of about 190 mw. most of this comes from the avdd33 supply. total power dissipation increases about 50% as the clock rate is increased to the maximum clock rate of 250 mhz. 350 310 270 230 190 150 p total (mw) 0 50 100 150 200 250 f dac (mhz) 06569-030 25 75 125 175 225 f out = dc f out = nyquist figure 39. ad9747 power dissipation vs. f dac 15 12 9 6 3 0 i dvdd33 (ma) 0 50 100 150 200 250 f dac (mhz) 06569-031 25 75 125 175 225 ad9747 ad9741 figure 40. dvdd33 current vs. f dac
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 26 of 28 30 24 18 12 6 0 i dvdd18 (ma) 0 50 100 150 200 250 f dac (mhz) 06569-032 25 75 125 175 225 ad9747 ad9741 figure 43 shows the power consumption for each power supply domain as well as the total power consumption. individual bars within each group display the powe r in full active mode (blue) vs. power for five increasing levels of power-down. 06569-045 p diss (mw) 0 50 100 150 200 250 300 350 avdd33 dvdd18 cvdd18 dvdd33 tot pwr full active dco off aux off dac off clk off bias off figure 41. dvdd18 current vs. f dac 15 13 11 9 7 5 i cvdd18 (ma) 0 50 100 150 200 250 f dac (mhz) 06569-033 25 75 125 175 225 figure 43. power dissipation vs. power-down mode the overall power consumption is dominated by avdd33 and significant power savings can be achieved simply by disabling the dac outputs. also, disabling the dac outputs is a signifi- cant way to conserve power and still maintain a fast wake-up time. full power-down disables all circuitry for minimum power consumption. note, however, that even in full power- down, there is a small power draw (25 mw) due to incoming data activity. to lower power consumption to near zero, all incoming data activity must be halted. figure 42. cvdd18 current vs. f dac
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 27 of 28 outline dimensions compliant to jedec standards mo-220-vnnd-3 042407-0 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0 .85 0 .80 0.05 max 0.02 nom seating plane 1 18 54 37 19 36 72 55 0.50 0.40 0.30 0.30 0.23 0.18 9.00 ref 0.60 max 0.60 max 4.70 bsc sq pin 1 indicator 0.50 bsc exposed pa d (bottom view) pin 1 indicator top view 9.75 bsc sq 10.00 bsc sq exposed pad must be soldered to pcb and connected to avss. figure 44. 72-lead lead frame chip scale package [lfcsp_vq] 10 mm 10 mm, very thin quad (cp-72-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9741bcpz 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 ad9741bcpzrl 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 AD9743bcpz 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 AD9743bcpzrl 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 ad9745bcpz 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 ad9745bcpzrl 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 ad9746bcpz 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 ad9746bcpzrl 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 ad9747bcpz 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 ad9747bcpzrl 1 ?40c to +85c 72-lead lfcsp_vq cp-72-1 ad9741-ebz 1 evaluation board AD9743-ebz 1 evaluation board ad9745-ebz 1 evaluation board ad9746-ebz 1 evaluation board ad9747-ebz 1 evaluation board 1 z = rohs compliant part.
ad9741/AD9743/ad9745/ad9746/ad9747 rev. 0 | page 28 of 28 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06569-0-5/07(0)

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